1. Field of the Invention
The present invention relates to a display panel driver and a display device including the display panel driver.
2. Description of the Related Art
Nowadays, thin flat display panels are increasing in size. In the field of television, particularly, even a liquid crystal panel exceeding 100-inch is present. This trend is considered to continue in the future. On the other hand, with the increase in size of liquid crystal panel, loads on data lines of TFT_LCD (Thin Film Transistor Liquid Crystal Display) are increased. Accordingly, an electric energy consumed by an amplifier of an LCD driver which drives TFT_LCD tends to increase.
With a view to reducing the number of LCD drivers used, the number of outputs from one chip is increased. Accordingly, the power consumption of one chip is increased, and thus the power consumption of the entire LCD driver is increased. The increase in the power consumption causes a problem that a temperature of the chip becomes abnormally high.
For this reason, a technique to reduce the power consumption in the LCD driver is required. In particular, a large number of amplifiers (operational amplifiers) are used in the LCD driver. Accordingly, if the power consumption in the amplifiers is reduced, the power consumption in the entire LCD driver can be greatly reduced.
For example, Japanese Patent Application Publication No. 2002-175052 describes an operational amplifier intended to reduce power consumption. Referring to FIGS. 1 to 3, an operational amplifier according to a conventional technique is described. FIG. 1 is a view showing the configuration of an operational amplifier circuit according to a conventional technique.
As shown in FIG. 1, the operational amplifier circuit according to the conventional technique includes differential input stage circuits 140, 240 supplied with a positive power supply voltage (VDD) and a negative power supply voltage (VSS), driving stage circuits 130, 230, switch circuits 30, 40, 50, 60, PMOS transistors MP180, MP280, and NMOS transistors MN180, MN280.
The driving stage circuit 130 is connected to an output terminal 110 via drains of the PMOS transistor MP180 and the NMOS transistor MN180. Similarly, the driving stage circuit 230 is connected to an output terminal 210 via drains of the PMOS transistor MP280 and the NMOS transistor MN280. The positive power supply voltage VDD is supplied to a, source of the PMOS transistor MP180 and a half of the positive power supply voltage (VDD/2) is supplied to a source of the NMOS transistor MN180. In addition, a half of the positive power supply voltage (VDD/2) is supplied to a source of the PMOS transistor MP280 and the negative power supply voltage VSS is supplied to a source of the NMOS transistor MN280.
The switch circuit 30 includes switches SW301 to SW304 and controls connections of the output terminals 110, 210 with an odd-numbered terminal 310 and an even-numbered terminal 320. The switch circuit 40 includes switches SW401 to SW404 and controls connections of terminals 410, 420 with input terminals 120, 220 respectively included in the differential input stage circuits 140, 240. Here, a positive voltage INP is inputted to the terminal 410 from a positive DAC (Digital Analog Converter), and a negative voltage INN is inputted to the terminal 420 from a negative DAC. The switch circuit 50 includes switches SW501 to SW504 and controls connections of the differential input stage circuits 140, 240 with the driving stage circuits 130, 230. The switch circuit 60 includes switches SW601 to SW604 and control connections of the output terminals 110, 210 with input terminals 121, 221 respectively included in the differential input stage circuits 140, 240.
By use of the switch circuits 30 to 60, the operational amplifier circuit according to the conventional technique can change the configuration of the amplifier circuit for driving the odd-numbered terminal 310 and the even-numbered terminal 320. Specifically, the configuration is changed by switching between pattern 1 and pattern 2. Here, in pattern 1, the switches SW301, SW303, SW401, SW403, SW501, SW503, SW601, SW603 are turned on, while the switches SW302, SW304, SW402, SW404, SW502, SW504, SW602, SW604 are turned off. In pattern 2, the odd-numbered switches are turned off while the even-numbered switches are turned on. In pattern 1, the positive voltage INP from the positive DAC is inputted to the amplifier circuit formed by the differential input stage circuit 140 and the driving stage circuit 130, and an output from the output terminal 110 is outputted to the odd-numbered terminal 310 as an odd-numbered output Vodd. At this time, the negative voltage INN from the negative DAC is inputted to the amplifier circuit including the differential input stage circuit 240 and the driving stage circuit 230, and an output from the output terminal 210 is outputted to the even-numbered terminal 320 as an even-numbered output Veven. On the other hand, in pattern 2, the positive voltage INP from the positive DAC is inputted to the amplifier circuit formed by the differential input stage circuit 240 and the driving stage circuit 130, and an output from the output terminal 110 is outputted to the even-numbered terminal 320 as an even-numbered output Veven. At this time, the negative voltage INN from the negative DAC is inputted to the amplifier circuit including the differential input stage circuit 140 and the driving stage circuit 230, and an output from the output terminal 210 is outputted to the odd-numbered terminal 310 as an odd-numbered output Vodd.
The operational amplifier circuit according to the conventional technique operates as described above to drive capacitive loads connected to the odd-numbered terminal 310 and the even-numbered terminal 320. At this time, the differential input stage circuits 140, 240 and the driving stage circuits 130, 230 operate within a voltage range from the positive power supply voltage VDD to the negative power supply voltage VSS, and the PMOS transistors MP180, MP280 and the NMOS transistors MN180, MN280 (output transistors) operates respectively within a voltage range from the positive power supply voltages VDD to VDD/2, and a voltage range from VDD/2 to VSS. With this configuration, power consumption of the output stage can be reduced by about half.
FIG. 2 is a view showing the configuration of the differential input stage circuit 140 according to the conventional technique. As shown in FIG. 2, the differential input stage circuit 140 includes: PMOS transistors MP103 to MP106 whose sources are supplied with a positive power supply voltage VDD; NMOS transistors MN103, MN104 whose sources are supplied with a negative power supply voltage VSS; NMOS transistors MN101, MN102 whose sources are connected to a negative power supply (VSS) via a constant current source I101; and PMOS transistors MP101, MP102 whose sources are connected to a positive power supply (VDD) via a constant current source I102.
The PMOS transistors MP101, MP102 form a differential pair and the NMOS transistors MN103, MN104 form active loads thereof. In addition, the NMOS transistors MN101, MN102 form a differential pair. The pair of the PMOS transistors MP104, MP105 and the pair of the NMOS transistors MN104, MN105 respectively form current mirror circuits, and outputs thereof are connected to drains of the NMOS transistors MN103, MN104, respectively. Furthermore, the input terminal 120 is connected to gates of the NMOS transistor MN101 and the PMOS transistor MP101, and the input terminal 121 is connected to gates of the NMOS transistor MN102 and the PMOS transistor MP102. Also, the drains of the NMOS transistor MN104 and the PMOS transistor MP106 are connected to the switches SW501, SW502 via the terminal 123.
With the configuration described above, differential input signals inputted to the input terminals 120, 121, and are converted into a single-ended input signal. Then, the resultant input signal is outputted from the terminal 123. The differential input stage circuit 240 has a similar configuration and similarly operates. Specifically, the input terminals 120, 121, the terminal 123, the switches SW501, SW502 of the differential input stage circuit 140 are respectively read as input terminals 220, 221, a terminal 223, and switches SW503, SW504 of the differential input stage circuit 240, respectively.
FIG. 3 is a view showing the configuration of the driving stage circuit 130 according to the conventional technique. As shown in FIG. 3, the driving stage circuit 130 includes: PMOS transistors MP107 to MP109 whose sources are supplied with a positive power supply voltage VDD; a NMOS transistor MN105 and a PMOS transistor MP110 whose sources are supplied with a negative power supply voltage VSS; and constant current sources 103, 104 which are supplied with a negative power supply voltage VSS. A gate of the NMOS transistor MN105 is connected to the switches SW501, SW502 via the terminal 131, and a drain of the NMOS transistor MN105 is connected to a drain of the PMOS transistor MP107. The PMOS transistor MP107, together with each of the PMOS transistors MP108, MP109, forms a current mirror circuit. A drain of the PMOS transistor MP108 is connected to the constant current source 103 via the PMOS transistor MP110. A gate of the PMOS transistor MP110 is connected to a gate of the PMOS transistor MP180. A drain of the PMOS transistor MP109 is connected to the gate of the NMOS transistor MP180 and the constant current source 104.
With the configuration described above, the driving stage circuit 130 receives an input voltage from the terminal 131 through the N-channel MOS transistor MN105, and provides outputs to drive the PMOS transistor MP180 and the NMOS transistor MN180. That is, a composite output signal according to the input signal from the terminal 131 is outputted to the terminal 110. The driving stage circuit 230 also has a similar configuration and similarly operates. Specifically, the PMOS transistor MP180, NMOS transistor MN180, terminal 131, switches SW501, SW503 of the driving stage circuit 130 are read as a PMOS transistor MP280, NMOS transistor MN280, terminal 231, and switches SW502, SW504 of the driving stage circuit 230, respectively.
In the differential input stage circuit 140 (240), the number of transistors differs between a current path where the differential pair of the NMOS transistors MN101, MN102 operate, and a current path where the differential pair of the PMOS transistors MP101, MP102 operate. Accordingly, the symmetry of the output characteristics of the driving stage circuits 130, 230 is lost. Here, as for the symmetry of the output characteristics, symmetry is regarded as excellent when a difference between a rise time and a fall time of an output pulse is small, while the symmetry is regarded as poor when a difference between a rise time and a fall time of an output pulse is large. For example, as shown in FIG. 4, a rise time Tr1 and a fall time Tf1 of a pulse in a positive output signal OUTP outputted to the odd-numbered terminal 310 (even-numbered terminal 320) show different values. When a capacitive load is driven by an output signal with such an asymmetric pulse form, charge and discharge characteristics for the capacitive load are deteriorated. There may be a case where such an operational amplifier circuit does not satisfy the specification of the LCD driver.
In addition, a relative accuracy between the transistors constituting the current mirror circuit is added when the differential pair of the PMOS transistors MP101, MP102 operates. Consequently, an offset voltage becomes large. This may deteriorate the characteristic of deviation of the circuit, when the circuit is used as the LCD driver.
Furthermore, a difference between a drain-source voltage of the PMOS transistor M P109 in the driving stage circuit 130 and a drain-source voltage of the PMOS transistor MP209 in the driving stage circuit 230 is approximately VDD/2. Because of this voltage difference and an output resistance in a pentode region, the drain currents of the PMOS transistors MP109, MP209 take different values from each other. In other words, the driving stage circuits 130, 230 show different output characteristics from each other.